Boundary ScanCore is a library of parameterized, synthesizable, register transfer level designs for board test automation, core test integration, test pattern reuse and embedded logic analysis. The library consists of two major Virtual Components (VC) - the Test Controller and the Boundary Scan Register. The test controller interfaces all on-chip test and debug circuitry to the 5 pin IEEE 1149.1 Test Access Port (TAP) interface. The test controller can be used to control any number of internal scan chains, internal clocks, Built-In Self-Test (BIST) circuits in a completely flexible manner without private user instructions. It also supports the reuse of core test patterns at the System-on-Chip (SoC) level. The boundary scan register provides controllability and observability of all chip pads at the board level. Several configurations of each VC are available which implement different feature sets. These VC´s are typically inserted at the top level of a SoC. Boundary ScanCore also includes parameterized self-checking testbenches which can be used for JTAG compliance checking, pin parametric test generation, at-speed scan chain testing, BIST logic testing and test vector generation in the WGL format